diff --git a/riscv/encoding.h b/riscv/encoding.h
index c109ce1..6931b39 100644
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -3,6 +3,8 @@
 #ifndef RISCV_CSR_ENCODING_H
 #define RISCV_CSR_ENCODING_H

+#define BARE_METAL_OUTPUT_CSR
+
 #define MSTATUS_UIE         0x00000001
 #define MSTATUS_SIE         0x00000002
 #define MSTATUS_HIE         0x00000004
@@ -783,6 +785,9 @@
 #define CSR_HPMCOUNTER29 0xc1d
 #define CSR_HPMCOUNTER30 0xc1e
 #define CSR_HPMCOUNTER31 0xc1f
+#ifdef BARE_METAL_OUTPUT_CSR
+#define CSR_BAREMETALOUTPUT 0x404
+#endif //bare metal output csr
 #define CSR_SSTATUS 0x100
 #define CSR_SIE 0x104
 #define CSR_STVEC 0x105
@@ -1451,6 +1456,9 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#ifdef BARE_METAL_OUTPUT_CSR
+DECLARE_CSR(bareMetalOutput, CSR_BAREMETALOUTPUT)
+#endif //BARE_METAL_OUTPUT_CSR
 #endif
 #ifdef DECLARE_CAUSE
 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 4a7d0ec..9ac2b8d 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -531,6 +533,11 @@ void processor_t::set_csr(int which, reg_t val)
     case CSR_DSCRATCH:
       state.dscratch = val;
       break;
+    #ifdef BARE_METAL_OUTPUT_CSR
+    case CSR_BAREMETALOUTPUT:
+      fprintf(stderr, "%c", ((int) val));
+      break;
+    #endif //bare metal output csr
   }
 }

@@ -556,6 +563,11 @@ reg_t processor_t::get_csr(int which)
   if (which >= CSR_MHPMEVENT3 && which <= CSR_MHPMEVENT31)
     return 0;

+  #ifdef BARE_METAL_OUTPUT_CSR
+  if (which == CSR_BAREMETALOUTPUT)
+    return 0;
+  #endif
+
   switch (which)
   {
     case CSR_FFLAGS: