This page is meant to describe each of the talks at the RISC-V workshop for those who are familiar with RISC-V. If you are not familiar with the RISC-V instruction set architecture (ISA), this page is probably not for you and you can learn about it here.
The RISC-V workshop took place in Barcelona from 7-9 May 2018. Please find more information and the slides on the RISC-V Workshop website.
Tutorial Day, 7 May
RISC-V ISA & Foundation Overview
Rick O'Connor, RISC-V Foundation
Foundation manages specifications and trademarks for showing a device is RISC-V compliant. NVIDIA and Western Digital will release cores
Andrew Waterman, SiFive
He described the following specs:
- 32-bit integer
- embedded (only 15 registers instead of 31)
- 64-bit integer
- multiply and divide
- floating point
- compressed (optimized for code density)
More details can be found on the RISC-V specification website.
RISC-V has 3 execution modes: machine, supervisor and user. The supervisor and user modes can also be virtualized in case of hypervisors. Interestingly, they said that although the specification v1.10 is still draft there is a low chance of changes being made that are not backward compatible. Please find more information on the RISC-V specification website or the workshop slides.
Daniel Lustig, NVIDIA
They have defined a memory model called RISC-V Weak Memory Order (RVWMO), which is easier to implement than total store ordering and easier for programmers than multi-copy-atomicity. In a nutshell RVWMO describes 13 patterns of two processor events for which program order is preserved. For more details on the 13 patterns please see the slides 26-35 of the talk.
The RISC-V Vector ISA
This spec is still in draft 32 additional vector registers with fixed number of elements. These registers can be interpreted as scalars, vectors or 2d matrices. Many additional instructions, for details please see the tutorial slides.
RISC-V Debug Spec Tutorial
Gajinder Panesar, UltraSoC
Basic features: select harts, halt/resume, abstract commands, program buffer, stepper etc. Debug adds a new execute mode that is above M (machine) mode Please find more information in the RISC-V debug spec GitHub.
Thomas Bourgeat, MIT
They work on a formal specification of the ISA (Instruction Set Architecture) and it is written in Haskell It is an alternative to the L3 and Sail models among others For more detail see the RISC-V Semantics GitHub
LLVM for RISC-V
Alex Bradbury lowRISC
This was a very nice tutorial in which he showed how to add custom instructions to the LLVM compiler. There is a quick/dirty solution of using a .insn directive and more complex solutions involving adding a .td file with using codegen for generating tests. I recommend looking at the slides on supporting custom instruction set extensions.
Workshop Day 1, 8 May
State of the Union
Krste Asonavic, SiFive
Very ambitions goal of wanting to be the industry standard ISA He stated that the following standards are in progress: formal, hyper-visor, vector, crypto, J (dynamic translation), P (packed SIMD) etc. They have a book for introducing RISC-V.
Vector ISA Proposal Update
Roger Espasa, Esperanto
The specification is nearly ready to be closed. For more details please see the slides on the Vector ISA Proposal Update.
State of RISC-V Software
Palmer Dabbelt, SiFive
There is a lot of activity for RISC-V software:
- OS porting: FreeBSD, Fedora and Debian are all being ported
- Compilers: LLVM, Clang, Go, OpenJDK
- Firmware: Berkeley boot loader, u-boot, UEFI etc.
- Simulation: Spike, rv8, Renode, QEMU
- Embedded support: Arduino, Platform.IO Important announcement here is that they are creating a RISC-V Platform Spec, defining profiles for systems like embedded, RTOS, Linux etc.
Formal Specification Technical Group
Rishiyur Nikhil, Bluespec
See formal specification section. Next steps: publish formal specification, merge formal ISA specification with memory model
RISC-V Memory Consistency Model
Dan Lustig, NVIDIA
Keynote: software drives hardware
Robert Oshana, VP Software Engineering at NXP
Robert talked about NXP's experience with using RISC-V in an industrial setting They like RISC-V because they can leverage the open-source ISA so that they can focus on their unique extensions Integrating RISC-V with ARM was initially a hard problem.
Keynote:enabling a new era of open data-centric computing architectures
Martin Fink, CTO at Western Digital
This presentation has pretty slides and cool buzzwords, I encourage you to take a look. Western Digital is doing RISC-V because it needs an open interface (not because of the ISA specifically) Patents play an increasing role for hardware design (as opposed to copyright in software)
Markus Goehrle, Lauterbach Engineering
Trace32 is Linux-aware and multi-core debugging software that works with any RISC-V compliant debug modules One big problem that they have is that there are quite a few custom debug implementations that are not compliant with the RISC-V debug spec
GDB in RISC-V
Jeremy Bennett, Embecosm
GDB has basic bare metal support for RISC-V since 6 March 2018
A common Software Development environment for many core RISC-V HW and virtual platforms
Simon Davidmann, Imperas
Imperas is a simulation solution that is:
- instruction accurate
- very fast: 100-2000 DMIPS
- full platform debugger (more than just GDB per core)
Yunsup Lee, SiFive
HiFive is a multi core RISC-V Linux dev board, which costs about $1000 SiFive allows you to make your own RISC-V SoC on their website and order it
HiFive unleashed expansion options and capabilities
Ted Marena, Microsemi
Mi-V focused on RTOS and is an extension board for the HiFive unleashed It adds peripheral support like PCIE and HDMI to HiFive
Simulating Heterogenous Multi-node RISC-V systems
Michael Gielda, Antmicro
Another simulation solution allowing multiple operating systems to be booted Find more information in their presentation
Debian Gnu/Linux Port for RISC-V 64 bit
Manuel Fernandez Montecelo, Debian
About 80% of Debian packages have been ported to RISC-V so far. Not yet available are: Firefox (no Rust) & Chromium (only x86 & ARM) If you're interested in checking the status of a debian package you can use the buildd website.
Fedora on RV
Richard Jones, Red Hat
Fedora is also progressing in their port. One interesting point that they made is that the RISC-V community should NOT couple too tightly Linux, also other OS's like Windows need to run if the ISA is to be successful
smallest RISC-V device
Seiji Munetoh, IBM
These guys built on top of the PULPino project and they were designing for next generation embedded devices. In the end they made a chip that is 300um by 250um with 2kB SRAM
Sergi Girona, Barcelona Supercomputing Center
This is a super computer installed in the university's chapel and has 13.7 Pflops/s. Besides Intel they also have emerging architectures like: Power9+NIVIDIA, ARMv8, KNH Some other stats: 394 TB RAM, 830 TB SSD, 1.5 MW, 14 PB disk storage They plan to include RISC-V in the future
Workshop Day 2, May 9
Krste Asanovic, SiFive
The current interrupt scheme disables interrupts while the handler is running, but some embedded applications require nested interrupts. For example, there might be an interrupt that needs handling before the one currently being handled. Additionally the new fast interrupt scheme would allow interrupt priorities. They have started up a working group to enable fast interrupts.
RISC-V DSP (P) Extension
Chuan-Hua Chang, Andes
Andes produces SoCs for diverse applications. They are going to head the DSP task group, which will be responsible for defining RISC-V extension for digital signal processing (DSP) applications.
Security task group
Richard Newell, Microsemi
Originally the security task group consisted of two projects: micro-controller trusted execution environments and cryptography. Now these are separate task groups and there is a new security charing committee. The new committee is headed by Helena Handschuh and Joseph Kiniry.
Formal Assurance for RV
Daniel Zimmerman, Galois
This talk was all about how to formally assure that an implementation fulfills the specification. The talk introduced LANDO which is a domain specific language that specifies architecture, correctness properties and security properties Lastly, the talk also talked about security and the difficulty in measuring security of an implementation
How to not specify things
Clifford Wolf, Symbiotic EDA
This talk argued that sometimes you don't want to specify all corner cases because it will make certain hardware less efficient OK ways to specify a hole in your system:
- Return an unspecified value.
- Return an implementation specific value.
- Return a specific value.
Foundational HPC Systems for 2020 and Beyond
Steven Wallach, Micron
This talk was about the RV128 specification and he introduced the idea of having the first 64 bits being an object identifier and the last 64 bits as the byte address.
Keynote: Barcelona Supercomputing Center
Mateo Valero, BSC
Memory bandwidth is more important than CPU power in supercomputing nowadays EU is currently not a big player in super computing as compared to US, Japan and China. EPI: European processor initiative wants to change that and they're pushing this to be RISC-V, although current proposal is ARM
Securing RISC-V processors from time speculation
Christopher Celio, Esperanto
This talk went into the detail of what is needed to do a cache side-channel attack and how to avoid them. Interesting ideas like partitioning the caches and selectively flushing them on a context switch. For details read the slides of this presentation.
Use of RISC-V on Pixel Visual Core
Matt Cockrell, Google
Matt talked about how they evaluated RISC-V for use in the image processing unit of their Pixel phone. They chose the PULP project as a base and he mentioned the importance of running lint tools and version control.
Charlie Su, Andes Technologies
AndeStar V5 architecture improves on standard RISC-V
- code size reduction on top of C
- cache management with finer granularity
Serious player building chips for real customers
Gajinder Panesar, UltraSoC
Sometimes debugging is not always possible and then tracing is necessary. For example a branch trace will define the complete control flow graph. At the moment this is custom built by UltraSoC, but they will set up a task group to standardize
RISC-V meet 22FDX
Pasquale Davide Schiavone, ETH Zurich Sanjay Charagulla, Global Foundries
PULP: open source ultra low power u-controller platform. They've built a RISC-V processor, but also the infrastructure around it like the memory system. Global foundries;
- Want to accelerate RISC-V development
- Implemented PULPissimo in their 22FDX process
Florian Zaruba, ETH Zurich
RISC-V support for persistent memory systems
Matheus Ogleari, Western Digital
Persisten memory is about having more control over what is written to disk, which means ways to:
- bypass the cache for stores and loads
- evict cache lines
- introducing memory barriers specifically to disk
An alternative is to use a bit in the page table to say uncacheable, but this is less flexible.
Hybrid threading processor for sparse data kernels
Tony Brewer, Micron
Problem: sparse data sets exceeding cache size Solution: hybrid threading, which moves threads around to the data that they need Micron is using RISC-V for prototyping hybrid threading with custom instructions
PULP-base platforms are helping security research
Frank Gurkaynak, ETH
This talk was about how PULP allows researchers to study hardware security. He described an implementation of leakage resilient cryptography and a way for control flow protection by using cryptographic sponges.
RISC-V virtual platform for early RISC-V embedded software developments
Lee Moore, Imperas & Ashling
Virtual platform accelerate software development, because you can simulate instructions before the hardware is ready