Dr Marno van der Maas
Creating a future of secure and private computing.
I'm passionate about silicon security, ranging from realizing trusted execution environments in computer architecture to designing full system on chips. Hardware security is the thread that connects my career from automotive networks to micro-architectural side-channel attacks to silicon roots of trust. The rest of this page goes through some of my career as well as talks I've given and publications I've made.
Since 2022, I have been working with lowRISC. We are working towards making open source silicon a reality, for example we are creating the first silicon root-of-trust that is open source and putting CHERIoT hardware in the hands of embedded systems engineers. Most of my work is open source and you can have a look on my GitHub profile to see what I work on. Here's a list of talks that I have given:
- Sonata: low-cost CHERI hardware for embedded systems @ State of Open Con 2024: slides and notes, conference page, video recording
- Fully verified open silicon @ Open Source Summit Europe 2023: slides and notes, conference page, video recording
- CHERIoT enablement @ TASER/CHES 2023: slides and notes, conference page
- Protecting enclaves from intra-core side-channel attacks through physical isolation @ CYSARM 2020: paper, video recording
From 2017 to 2022, I attained my PhD in Computer Science at the University of Cambridge. My PhD is on making it possible for applications to keep data private from the rest of the system, even the operating system they run on top of. Enclave systems provide such protection from operating systems or other privileged code. However, previous work has done little to protect enclaves against side-channel attacks. Side-channel attacks are attacks that infer information about applications based on side effects like timing. To protect against such side-channel attacks, I explored physically isolating enclaves onto separate cores and have successfully published a paper on this topic, which is titled Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation. We published this paper at CYSARM 2020, which is co-located with ACM CCS 2020.
Here's a list of my publications:
- 2024, paper: Randomized Testing of RISC-V CPUs Using Direct Instruction Injection
- 2023, paper: Architectural Contracts for Safe Speculation
- 2023, technical report: Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 9)
- 2023, technical report: Protecting enclaves from side-channel attacks through physical isolation
- 2023, extended abstract: Developing an open-source silicon ecosystem: the silicon commons
- 2023, extended abstract: Verifying enhanced PMP behavior in Ibex
- 2022, thesis: Protecting enclaves from side-channel attacks through physical isolation
- 2020, paper: Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation
- 2019, patent: Method for provisioning a device with a verified and diversified public key
- 2019, patent: Node, a vehicle, an integrated circuit and method for updating at least one rule in a controller area network
- 2017, patent: Controller area network (CAN) message filtering
Between 2014 and 2017, I worked for NXP semiconductors in the area of automotive security. I worked on improving the security of in-vehicle networks and car-to-car communication.